1. Field of the Invention
The present invention relates generally to digital circuits and, particularly, to a digital random noise generator system and methodology.
2. Discussion of the Prior Art
It is common in today's highly integrated semiconductor circuit technologies to identify chip function failures caused by the presence of noise. Most noise problems are found in multi-system chips that include analog, digital, and hybrid mixed-signal circuits. For example, a digital circuit such as a microprocessor chip may produce a significant amount of switching noise, for instance, when a clock frequency of that chip exceeds the GHz range. Such a hostile environment adversely degrades the performance of other (mostly analog) circuit systems. As another example, in a high-density memory chip, significant noise is generated by thousands of sense amplifiers switching simultaneously when a row is accessed. Furthermore, noise generated when hundreds of off-chip drivers that simultaneously switch between ground and Vdd, i.e., bounce, due to sudden change in current flow (dI/dt), become a concern for noise sensitive circuits. As another example, devices built on a structure comprising a thin lightly doped epitaxial layer on top of a heavily doped layer that are commonly used to prevent a latch-up related problem, become susceptible to the coupling noise through the substrate.
Noise sensitive circuits are not just limited to the analog circuits. Dynamic logic circuits, those that utilize precharge/predischarge technique, single-ended direct sensing circuits, and area-limiting circuits having floating nodes, etc. are all susceptible to noise disturbance. At the same time, the dynamic circuits themselves also create certain degree of noise due to the simultaneous precharging and discharging action. Achievement of a quiet chip neighborhood is thus an ideal situation, however, is increasingly becoming less realistic in current real chip designs.
There currently exist techniques for testing a circuit's noise immunity. Test macro and analyzing circuits usually small, low density, are mostly operated individually and typically require a noise generator. That is, a semiconductor noise generator is needed for generating noise in order to evaluate newly designed circuits, especially for those circuits which are believed to be noise sensitive. In a testing operation, the noise generator is implemented nearby a test circuit in order to provide the test macro with an artificial switch noise, e.g., for mimicking the noise on the real chip environment.
In order to ensure the circuits function as if operating in real life, noise sensitive circuits must survive creation noise disturbance that the circuit may be subject to while operating in real life. Thus it would be highly desirable that the noise generator, its noise pattern and magnitude must be made configurable, so that a full noise analysis at different noise backgrounds may be carried out.
Furthermore, it would be desirable that the noise generator be small in size, yet permit the degree of the noise, i.e., its magnitude and frequency, to be made tuneable. This would enable one noise generator to be repeatedly used by many different test circuits to mimic different environments. Furthermore, it would additionally be desirable to provide a random noise pattern so that the test circuits may be tested under a situation very close to the real chip operating condition.
U.S. Pat. No. 5,668,507 entitled “Noise generator for evaluating mixed signal integrated circuits” describes a noise generator device comprising a programmable oscillator generating noise signal having a predetermined frequency. It further comprises a programmable load buffer circuit to tune the magnitude of the noise signal. The programmability for this device is accomplished by tapping the capacitor load of a ring oscillator so that the frequency will be altered. The stage of the ring oscillator in this device is also made programmable so that the frequency of the noise can be altered. In addition, the size of the devices may also be changed to cause the frequency of the oscillator and thus the frequency of the noise to change. It provides both coarse and fine tune capabilities to tune the noise frequency. Additionally, in this prior art description, frequency divider circuits are used to divide the frequency.
In the device described in U.S. Pat. No. 5,668,507, the resulting noise pattern has a rather regular format, i.e., the noise has a frequency and magnitude which may vary in specific, or predetermined ranges. In the real chips, such a noise pattern is unlikely to occur, especially for asynchronous circuit designs.
Therefore, it is highly desirable to provide a random noise generator circuit capable of generating a random, or at least pseudo random, noise pattern for noise study, wherein the random noise is defined as a noise pattern having no detectable frequency or magnitude.